The Verigy 93000 (93k) SOC Series remains a cornerstone of Automated Test Equipment (ATE) for high-performance semiconductors. Navigating its extensive documentation is essential for test engineers looking to optimize throughput and maintain signal integrity. This guide provides a strategic overview of the Verigy 93k tester manual, focusing on the SmarTest environment, hardware configurations, and troubleshooting protocols. Understanding the Verigy 93k Architecture
To ensure repeatable results across different testers, the Verigy 93k manual emphasizes strict calibration routines.
Measuring setup/hold times and propagation delays. Advanced Troubleshooting Tips verigy 93k tester manual
The first line of defense to ensure the DUT is seated correctly. DC Parametrics: Measuring leakage currents ( IILcap I sub cap I cap L end-sub IIHcap I sub cap I cap H end-sub ) and power consumption ( IDDQcap I sub cap D cap D cap Q end-sub
Providing the mechanical interface to probers or handlers. SmarTest Software Environment The Verigy 93000 (93k) SOC Series remains a
The 93k uses an equation-based timing system. Instead of hard-coding values, engineers use variables to define cycle times and edge placements, allowing for easy frequency scaling during characterization.
Executing patterns at speed to verify logic gates. DC Parametrics: Measuring leakage currents ( IILcap I
The manual typically divides the system into several key components: Running the SmarTest software environment.
Containing the pin electronics and cooling systems.
Used for high-precision applications, this calibrates specific pins to the Device Under Test (DUT) interface board level, compensating for traces and socket parasitics.